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Experiences from Adjusting Industrial Software for Worst-Case Execution Time Analysis.

, , , , and . ISORC, page 62-70. IEEE, (2021)

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Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation., , , , , and . IEEE Trans. Ind. Informatics, 8 (2): 366-377 (2012)Leros: A Tiny Microcontroller for FPGAs.. FPL, page 10-14. IEEE Computer Society, (2011)Towards Dual-Issue Single-Path Code., , and . ISORC, page 176-183. IEEE, (2020)Hardlock: A Concurrent Real-Time Multicore Locking Unit., and . ISORC, page 9-16. IEEE Computer Society, (2018)Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor., and . ISORC, page 268-271. IEEE Computer Society, (2015)Restrictions of Java for Embedded Real-Time Systems.. ISORC, page 93-100. IEEE Computer Society, (2004)A Single-Path Chip-Multiprocessor System., , and . SEUS, volume 5860 of Lecture Notes in Computer Science, page 47-57. Springer, (2009)A Time Predictable Instruction Cache for a Java Processor.. OTM Workshops, volume 3292 of Lecture Notes in Computer Science, page 371-382. Springer, (2004)Exhaustive testing of safety critical Java., , , and . JTRES, page 164-174. ACM, (2010)A Fault-Tolerant Time-Predictable Processor., and . NORCAS, page 1-6. IEEE, (2019)