Author of the publication

A Network Traffic Generator Model for Fast Network-on-Chip Simulation.

, , , , , and . DATE, page 780-785. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip., , and . CODES+ISSS, page 481-490. ACM, (2009)Demonstration of a Time-predictable Flight Controller on a Multicore Processor., , , , , , and . ISORC, page 95-96. IEEE, (2019)Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements., , and . DSD, page 168-175. IEEE, (2023)An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip., , , and . SoC, page 171-174. IEEE, (2005)ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology., and . NOCS, page 55-64. IEEE Computer Society, (2008)Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools., , , and . NORCHIP, page 1-6. IEEE, (2014)Interfacing hardware accelerators to a time-division multiplexing network-on-chip., , , and . NORCAS, page 1-4. IEEE, (2015)An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures., , , , and . IEEE J. Solid State Circuits, 26 (2): 90-97 (February 1991)A Time-Predictable Memory Network-on-Chip., , , and . WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting., , , , , , , , and . MLSP, page 1-6. IEEE, (2023)