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Diagnosis and Correction of Logic Design Errors in Digital Circuits.

, , and . DAC, page 503-508. ACM Press, (1993)

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Estimation of state line statistics in sequential circuits., , and . ACM Trans. Design Autom. Electr. Syst., 7 (3): 455-473 (2002)High-performance bidirectional repeaters., and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2000)An optimization technique for dual-output domino logic., , and . ISLPED, page 258-260. ACM, (1999)Post-Route Gate Sizing for Crosstalk Noise Reduction., , , , , , and . ISQED, page 171-176. IEEE Computer Society, (2003)A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model., and . ISQED, page 133-138. IEEE Computer Society, (2001)An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling., and . ISQED, page 51-58. IEEE Computer Society, (2000)An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications., and . Great Lakes Symposium on VLSI, page 68-. IEEE Computer Society, (1999)Maximum Current Estimation in Programmable Logic Arrays., and . Great Lakes Symposium on VLSI, page 301-306. IEEE Computer Society, (1998)Computation of bus current variance for reliability estimation of VLSI circuits., , and . ICCAD, page 202-205. IEEE Computer Society, (1989)ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits., and . ITC, page 742-751. IEEE Computer Society, (1992)