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A new voltage binning technique for yield improvement based on graph theory.

, , and . ISQED, page 243-248. IEEE, (2012)

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SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits., , , and . DAC, page 158-161. IEEE, (2007)DeMOR: decentralized model order reduction of linear networks with massive ports., , , , and . DAC, page 409-414. ACM, (2008)Compact nonlinear thermal modeling of packaged integrated systems., , , , and . ASP-DAC, page 157-162. IEEE, (2013)GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver., and . ASP-DAC, page 719-724. IEEE, (2015)Data-Driven Electrostatics Analysis based on Physics-Constrained Deep learning., , and . DATE, page 1382-1387. IEEE, (2021)EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs., , and . ICCAD, page 146-151. IEEE, (2015)From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance., , and . ICCAD, page 457-464. IEEE, (2015)HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural Network., , , , and . ICCAD, page 28:1-28:9. ACM, (2022)Partial random walk for large linear network analysis., , , and . ISCAS (5), page 173-177. IEEE, (2004)An efficient statistical chip-level total power estimation method considering process variations with spatial correlation., , and . ISQED, page 671-676. IEEE, (2011)