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Deterministic Clock Gating for Microprocessor Power Reduction.

H. Li, S. Bhunia, Y. Chen, T. Vijaykumar, and K. Roy. HPCA, page 113-122. IEEE Computer Society, (2003)

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Yiran Wang

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Other publications of authors with the same name

Stable and Causal Inference for Discriminative Self-supervised Deep Visual Representations.Y. Yang, H. Li, and Y. Chen. ICCV, page 16063-16074. IEEE, (2023)FedMask: Joint Computation and Communication-Efficient Personalized Federated Learning via Heterogeneous Masking.A. Li, J. Sun, X. Zeng, M. Zhang, H. Li, and Y. Chen. SenSys, page 42-55. ACM, (2021)APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.Z. Xie, X. Xu, M. Walker, J. Knebel, K. Palaniswamy, N. Hebert, J. Hu, H. Yang, Y. Chen, and S. Das. MICRO, page 1-14. ACM, (2021)NASRec: Weight Sharing Neural Architecture Search for Recommender Systems.T. Zhang, D. Cheng, Y. He, Z. Chen, X. Dai, L. Xiong, F. Yan, H. Li, Y. Chen, and W. Wen. WWW, page 1199-1207. ACM, (2023)Neural Predictor for Neural Architecture Search.W. Wen, H. Liu, H. Li, Y. Chen, G. Bender, and P. Kindermans. CoRR, (2019)Self-Trained Proposal Networks for the Open World.M. Inkawhich, N. Inkawhich, H. Li, and Y. Chen. CoRR, (2022)FedBPT: Efficient Federated Black-box Prompt Tuning for Large Language Models.J. Sun, Z. Xu, H. Yin, D. Yang, D. Xu, Y. Chen, and H. Roth. CoRR, (2023)Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.B. Zhao, J. Yang, Y. Zhang, Y. Chen, and H. Li. ACM Trans. Design Autom. Electr. Syst., 18 (4): 57:1-57:18 (2013)Memristive LSTM Network for Sentiment Analysis.S. Wen, H. Wei, Y. Yang, Z. Guo, Z. Zeng, T. Huang, and Y. Chen. IEEE Trans. Syst. Man Cybern. Syst., 51 (3): 1794-1804 (2021)Introduction to the Special Issue on Hardware and Algorithms for Efficient Machine Learning - Part 2.Y. Chen, Q. Qiu, and Y. Lin. ACM J. Emerg. Technol. Comput. Syst., 17 (4): 45:1-45:2 (2021)

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Disambiguation of "Chen, Yiran"

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Deterministic Clock Gating for Microprocessor Power Reduction.

Please choose a person to relate this publication to

Yiran Wang

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Yiran"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Deterministic Clock Gating for Microprocessor Power Reduction.

Please choose a person to relate this publication to

Yiran Wang

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Deterministic Clock Gating for Microprocessor Power Reduction.