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On-Chip Verification of NoCs Using Assertion Processors., , , , and . DSD, page 535-538. IEEE Computer Society, (2007)GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks., , and . ReCoSoC, page 1-5. IEEE, (2012)Transport layer aware design of network interface in many-core systems., , , and . ReCoSoC, page 1-7. IEEE, (2012)FPGA implementation of AES-based crypto processor., , , , and . ICECS, page 369-372. IEEE, (2013)An exploration of heterogeneous systems., , , and . ReCoSoC, page 1-7. IEEE, (2013)Optimizing scheduling for heterogeneous computing systems using combinatorial meta-heuristic solution., , , and . SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, page 1-8. IEEE, (2017)Automated Power and Latency Management in Heterogeneous 3D NoCs., , , and . NoCArc@MICRO, page 33-38. ACM, (2015)Smart hill climbing for agile dynamic mapping in many-core systems., , , and . DAC, page 39:1-39:6. ACM, (2013)Fault-tolerant 3-D network-on-chip design using dynamic link sharing., , , and . DATE, page 1195-1200. IEEE, (2016)High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems., , and . PDP, page 462-469. IEEE Computer Society, (2013)