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A pattern based instruction encoding technique for high performance architectures.

, , and . Int. J. High Perform. Syst. Archit., 2 (2): 71-80 (2009)

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Wear-out analysis of Error Correction Techniques in Phase-Change Memory., , , and . DATE, page 1-4. European Design and Automation Association, (2014)AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction., , and . ACM Trans. Archit. Code Optim., 15 (4): 49:1-49:30 (2019)Bringing Energy Information to the Instruction Set., , , and . SBESC, page 1-8. IEEE, (2020)Prof5: A RISC-V profiler tool., , , , , , , and . SBAC-PAD, page 201-210. IEEE, (2022)Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory., , and . SBAC-PAD, page 68-77. IEEE, (2023)High-Level Switching Activity Prediction Through Sampled Monitored Simulation., , and . SoC, page 161-166. IEEE, (2005)Multi-profile based code compression., , , and . DAC, page 244-249. ACM, (2004)A SystemC profiling framework to improve fixed-point hardware utilization., , , and . SBCCI, page 1-6. IEEE, (2020)Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures., , , and . CASES, page 141-148. ACM, (2001)DONUTS: An efficient method for checkpointing in non-volatile memories., , and . Concurr. Comput. Pract. Exp., (2023)