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SRAM Local Bit Line Access Failure Analyses.

, , , , , и . ISQED, стр. 204-209. IEEE Computer Society, (2006)

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Praveen Konidala

Paurush Praveen

Praveen Seshadri

Praveen Kulkarni

Praveen Kumar

 

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DG-SRAM: a low leakage memory circuit., , и . SoCC, стр. 167-170. IEEE, (2005)Leakage Reduction for Domino Circuits in Sub-65nm Technologies., , и . SoCC, стр. 164-167. IEEE, (2006)RG-SRAM: A Low Gate Leakage Memory Design., , и . ISVLSI, стр. 295-296. IEEE Computer Society, (2005)A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs., , , и . VLSI Design, стр. 130-133. IEEE Computer Society, (2005)Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits., , и . J. Low Power Electron., 1 (2): 182-193 (2005)Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM).. ISQED, стр. 8-9. IEEE Computer Society, (2008)High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach., , и . VLSI Design, стр. 569-574. IEEE Computer Society, (2006)Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level., , и . SoCC, стр. 79-82. IEEE, (2007)Leakage aware SER reduction technique for UDSM logic circuits., , , и . SoCC, стр. 82-85. IEEE, (2004)Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic., , и . ISQED, стр. 617-624. IEEE Computer Society, (2006)