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Disambiguation of "Mohapatra, Satyajit"

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A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.

, , , , , and . VLSID, page 305-310. IEEE, (2019)

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Satyajit Rao

Chittaranjan Mohapatra

Dushmanta Mohapatra

Goutam Mohapatra

Durga Prasanna Mohapatra

 

Other publications of authors with the same name

An Ensemble Approach for Annotating Source Code Identifiers with Part-of-speech Tags., , , , , , , , , and . CoRR, (2021)Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications., , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 590-604. Springer, (2019)A 64b/66b Line Encoding for High Speed Serializers., , , and . VLSID, page 303-308. IEEE Computer Society, (2017)Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices., , and . VDAT, volume 711 of Communications in Computer and Information Science, page 56-61. Springer, (2017)The HotSpot Compensation in High Speed Data Converters., and . MWSCAS, page 396-399. IEEE, (2018)Re-Max: A Reward Maximization Approach for Heterogeneous Drone Scheduling Problem., and . ICDCN, page 242-243. ACM, (2024)The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD)., and . VLSID, page 72-77. IEEE, (2020)Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array., , , and . ISQED, page 462-467. IEEE, (2016)Greedy Algorithms for Heterogeneous Drone Delivery Packing in the Cloud-assisted Intelligent Transportation System., and . COMSNETS, page 833-841. IEEE, (2024)Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS., , and . ISVLSI, page 175-180. IEEE Computer Society, (2018)