Author of the publication

Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition.

, and . ISCAS, page 2910-2913. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT., and . APCCAS, page 458-461. IEEE, (2006)Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series., , and . iSES, page 312-315. IEEE, (2019)High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (7): 606-610 (2007)Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder., and . ASAP, page 305-309. IEEE Computer Society, (2008)Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms.. ASAP, page 97-101. IEEE Computer Society, (2008)Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform., and . ASAP, page 43-48. IEEE Computer Society, (2008)A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors., , and . ISCAS, page 1-5. IEEE, (2024)Efficient Bit-Parallel Multipliers in Composite Fields., and . APSCC, page 686-691. IEEE Computer Society, (2008)Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform., , and . ISCAS, page 1480-1483. IEEE, (2012)Flexible integer DCT architectures for HEVC., and . ISCAS, page 1376-1379. IEEE, (2013)