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Другие публикации лиц с тем же именем

Efficient Bit-Parallel Multipliers in Composite Fields., и . APSCC, стр. 686-691. IEEE Computer Society, (2008)Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series., , и . iSES, стр. 312-315. IEEE, (2019)High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation., , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (7): 606-610 (2007)Flexible integer DCT architectures for HEVC., и . ISCAS, стр. 1376-1379. IEEE, (2013)Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic., , и . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition., и . ISCAS, стр. 2910-2913. IEEE, (2009)Efficient coefficient partitioning for decomposed DA-based inner-product computation., и . ISCAS, стр. 406-409. IEEE, (2011)VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT., и . APCCAS, стр. 458-461. IEEE, (2006)Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT., и . IEEE Trans. Circuits Syst. Video Techn., 23 (2): 353-363 (2013)An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials., , и . ASP-DAC, стр. 210-215. IEEE, (2009)