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A Low-Power Highly Linear CMOS Transconductance Topology., , and . ICECS, page 620-623. IEEE, (2006)A very low-noise low-power integrator for high-resolution ΔΣ modulators., , and . ICECS, page 802-805. IEEE, (2003)A new structure for capacitor-mismatch-insensitive multiply-by-two amplification., , and . ISCAS, IEEE, (2006)On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulators., and . ISCAS (3), page 2547-2550. IEEE, (2005)Continuous time delta sigma modulators with reduced clock jitter sensitivity., and . ISCAS, IEEE, (2006)A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch., , and . ISCAS (2), page 1409-1412. IEEE, (2005)Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique., , , and . ISCAS (1), page 220-223. IEEE, (2005)High power factor wireless power transfer front-end circuit for heterogeneous systems., , , and . MWSCAS, page 444-447. IEEE, (2017)A new compensation technique for two-stage CMOS operational transconductance amplifiers., , , and . ICECS, page 539-542. IEEE, (2003)A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (9): 2883-2896 (2020)