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Incremental Sturdy-MASH Sigma-Delta Modulator with Reduced Sensitivity to DAC Mismatch.

, , , and . ISCAS, page 1-5. IEEE, (2019)

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Incremental Sturdy-MASH Sigma-Delta Modulator with Reduced Sensitivity to DAC Mismatch., , , and . ISCAS, page 1-5. IEEE, (2019)A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 57 (11): 3407-3417 (2022)A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR., , , , and . ESSCIRC, page 401-404. IEEE, (2023)A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators., , , and . ISCAS, page 1-5. IEEE, (2020)A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators., , , and . ICECS, page 1-4. IEEE, (2021)FIR DACs in CT Incremental Delta-Sigma Modulators., , , , and . ISCAS, page 1-5. IEEE, (2020)A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta-Sigma Modulator With Differentially Reset FIR Feedback., , , and . ESSCIRC, page 87-90. IEEE, (2019)A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS., , , , , and . CICC, page 1-2. IEEE, (2021)Automated Design of Sigma-Delta Modulators with FIR Feedback., , and . ISCAS, page 571-575. IEEE, (2022)End-user's SLA-aware consolidation in cloud data centers., , , , and . ISSPIT, page 196-204. IEEE Computer Society, (2017)