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DAC linearity improvement with layout technique using magic and latin squares., , , , , , , and . ISPACS, page 616-621. IEEE, (2017)Estimation of circuit component values in buck converter using efficiency curve., , , and . ISPACS, page 895-900. IEEE, (2017)Architecture of high performance successive approximation time digitizer., , , , , , , , and . ISPACS, page 456-461. IEEE, (2017)Study of jitter generators for high-speed I/O interface jitter tolerance testing., , , , and . ISPACS, page 468-473. IEEE, (2017)Delay-time suppression technique for DC/DC buck converter using voltage mode PWM control., , , , , and . ISPACS, page 758-763. IEEE, (2017)A Study on Loop Gain Measurement Method Using Output Impedance in DC-DC Buck Converter., , and . IEICE Trans. Commun., 101-B (9): 1940-1948 (2018)SAR TDC Architecture with Self-Calibration Employing Trigger Circuit., , , , , , , and . ATS, page 94-99. IEEE Computer Society, (2017)Two-phase soft-switching DC-DC converter with voltage-mode resonant switch., , , , and . ISPACS, page 735-740. IEEE, (2017)EMI reduction technique with noise spread spectrum using swept frequency modulation for hysteretic DC-DC converters., , , , , and . ISPACS, page 889-894. IEEE, (2017)Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit., , , , , , , , , and 3 other author(s). ISOCC, page 137-138. IEEE, (2020)