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Disambiguation of "Miura, Yukiya"

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Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.

, , and . Asian Test Symposium, page 121-126. IEEE Computer Society, (1999)

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Naotomo Miura

Kota Miura

Yuzuru Miura

 

Other publications of authors with the same name

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits., , and . Asian Test Symposium, page 120-124. IEEE Computer Society, (2000)Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection., and . Asian Test Symposium, page 119-124. IEEE Computer Society, (2012)Current Testable Design of Resistor String DACs., , , , and . ATS, page 399-403. IEEE, (2007)Development of FF Circuits for Measures Against Power Supply Noise., , and . IOLTS, page 48-51. IEEE, (2019)Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution., , , and . GECCO Companion, page 1956-1962. ACM, (2023)Simulation-based analysis of FF behavior in presence of power supply noise., and . IOLTS, page 151-156. IEEE, (2017)LSI aging estimation using ring oscillators., and . ETS, page 1-2. IEEE, (2015)A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit., , and . ISCAS, page 77-80. IEEE, (1994)Ramp Voltage Testing for Detecting Interconnect Open Faults.. IEICE Trans. Inf. Syst., 91-D (3): 700-705 (2008)Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits.. LATW, page 118-125. IEEE, (2001)