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Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results.

, , , and . HPCA, page 84-93. IEEE Computer Society, (1997)

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Compiler technology for future microprocessors., , , , , , , and . Proc. IEEE, 83 (12): 1625-1640 (1995)Compiler Code Transformations for Superscalar-Based High Performance Systems., , , and . SC, page 808-817. IEEE Computer Society, (1992)Code scheduling for VLIW/superscalar processors with limited register files., and . MICRO, page 197-201. ACM / IEEE Computer Society, (1992)Enabling Region Merging Optimizations in OpenMP., , , , and . IWOMP, volume 9342 of Lecture Notes in Computer Science, page 177-188. Springer, (2015)Trimaran: An Infrastructure for Research in Instruction-Level Parallelism., , , , , and . LCPC, volume 3602 of Lecture Notes in Computer Science, page 32-41. Springer, (2004)Speculative execution exception recovery using write-back suppression., , , , and . MICRO, page 214-223. ACM / IEEE Computer Society, (1993)A study of the cache and branch performance issues with running Java on current hardware platforms., , , , and . COMPCON, page 211-216. IEEE Computer Society, (1997)Tool Gear: Infrastructure for Parallel Tools., and . PDPTA, page 231-240. CSREA Press, (2003)An Efficient Framework for Performing Execution-Constraint-Sensitive Transformations That Increase Instruction-Level Parallelism. University of Illinois Urbana-Champaign, USA, (1997)Enabling rapid COVID-19 small molecule drug design through scalable deep learning of generative models., , , , , , , , , and 2 other author(s). Int. J. High Perform. Comput. Appl., (2021)