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On the credibility of load-latency measurement of network-on-chips., , and . SoC, page 1-7. IEEE, (2008)IP Integration Overhead Analysis in System-on-Chip Video Encoder., , , and . DDECS, page 333-336. IEEE Computer Society, (2007)HIBI-based multiprocessor SoC on FPGA., , and . ISCAS (4), page 3351-3354. IEEE, (2005)Evaluating SoC Network Performance in MPEG-4 Encoder., , , and . J. Signal Process. Syst., 56 (2-3): 105-123 (2009)Towards Dependable RISC-V Cores for Edge Computing Devices., , , , , , , , , and . IOLTS, page 1-7. IEEE, (2023)Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder., , , , and . DDECS, page 59-64. IEEE Computer Society, (2006)FPGA-Powered 4K120p HEVC Intra Encoder., , , , and . ISCAS, page 1-5. IEEE, (2018)Low Latency Edge Rendering Scheme for Interactive 360 Degree Virtual Reality Gaming., , , and . ICDCS, page 1557-1560. IEEE Computer Society, (2018)Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC., , , and . EURASIP J. Embed. Syst., (2006)Scalable multiprocessor system-on-chip architecture design on FPGA.. University of Tampere, Finland, (2009)base-search.net (ftunivtampere:oai:trepo.tuni.fi:10024/114283).