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Disambiguation of "Hellings, Geert"

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Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).

, , , , , , , , , , , , , , , and . IRPS, page 1-7. IEEE, (2023)

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Ulrich Hellings

Hans Hellings

Kai Marc Geertsema

Jakob Geerthsen

Philipp Geertsen

 

Other publications of authors with the same name

ESD characterisation of a-IGZO TFTs on Si and foil substrates., , , , , , , , and . ESSDERC, page 276-279. IEEE, (2017)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , and 5 other author(s). VLSIC, page 222-. IEEE, (2015)ESD characterization of planar InGaAs devices., , , , , , , , , and 7 other author(s). IRPS, page 3. IEEE, (2015)ESD protection diodes in optical interposer technology., , , , , , and . ICICDT, page 1-4. IEEE, (2015)Processing active devices on Si interposer and impact on cost., , , , , , , , , and . 3DIC, page TS11.2.1-TS11.2.4. IEEE, (2015)ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology., , , , and . ESSDERC, page 194-197. IEEE, (2018)Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology., , , , , , , , and . ESSDERC, page 265-268. IEEE, (2022)Scaling CMOS beyond Si FinFET: an analog/RF perspective., , , , , , , , , and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5)., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)Comphy - A compact-physics framework for unified modeling of BTI., , , , , , , , , and 4 other author(s). Microelectron. Reliab., (2018)