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A novel yield aware multi-objective analog circuit optimization tool., , , , и . ISCAS, стр. 2652-2655. IEEE, (2015)A hierarchical design automation concept for analog circuits., , , и . ICECS, стр. 133-136. IEEE, (2016)Design of a Low-power Ultrasound Transceiver for Underwater Sensor Networks., , , и . PRIME, стр. 129-132. IEEE, (2018)Circuit Design Techniques for High-Voltage Comparators and Amplifiers., и . CICC, стр. 1-8. IEEE, (2024)Exploring the unknown through successive generations of low power and low resource versatile agents., , , , , , , , и . DATE, стр. 290-293. IEEE, (2017)Post-Silicon Validation of Yield-Aware Analog Circuit Synthesis., , и . SMACD, стр. 245-248. IEEE, (2019)A -81.6dBm Sensitivity Ultrasound Transceiver in 65nm CMOS for Symmetrical Data-Links., , , и . ESSCIRC, стр. 145-148. IEEE, (2019)A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool., , , , и . DATE, стр. 1225-1228. ACM, (2015)A two-step layout-in-the-loop design automation tool., , , , , , и . NEWCAS, стр. 1-4. IEEE, (2015)