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Disambiguation of "Nakura, Toru"

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An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.

, , , , and . DDECS, page 131-136. IEEE Computer Society, (2015)

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Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ulrike Torunsky

 

Other publications of authors with the same name

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board., , , , , , and . ITC, page 1-8. IEEE, (2016)An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator., , , and . CICC, page 1-4. IEEE, (2013)Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (2): 410-424 (2018)Extension of power supply impedance emulation method on ATE for multiple power domain., , , , , , and . ETS, page 1-2. IEEE, (2017)On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure., , , , , and . ESSCIRC, page 183-186. IEEE, (2011)A Pulse Width controlled PLL and its automated design flow., , , and . ICECS, page 5-8. IEEE, (2013)Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects., , and . DDECS, page 167-172. IEEE Computer Society, (2010)Analytical design optimization of sub-ranging ADC based on stochastic comparator., , , and . DATE, page 517-522. IEEE, (2016)Cascaded Time Difference Amplifier with Differential Logic Delay Cell., , , , and . IEICE Trans. Electron., 94-C (4): 654-662 (2011)One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise., , , and . EWME, page 1-3. IEEE, (2016)