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40-Gb/s circuits built from a 120-GHz fT SiGe technology., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 37 (9): 1106-1114 (2002)29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 482-483. IEEE, (2017)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration., , , , , , , , , and 1 other author(s). CICC, page 1-8. IEEE, (2024)F5: Advanced optical communication: From devices, circuits, and architectures to algorithms., , , , , and . ISSCC, page 514-516. IEEE, (2018)A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array., , , , , , , , , and 4 other author(s). OFC, page 1-3. IEEE, (2015)Internet of the Body and Cognitive Hypervisor., , , , , , , , , and 9 other author(s). CHASE, page 296-297. IEEE Computer Society / ACM, (2017)FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS., , , , , , , , , and 1 other author(s). OFC, page 1-3. IEEE, (2018)A 25 Gb/s burst-mode receiver for low latency photonic switch networks., , , , , , , and . OFC, page 1-3. IEEE, (2015)A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2015)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)