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Disambiguation of "Morimoto, Masao"

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12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM.

, , , and . VLSI Circuits, page 19-20. IEEE, (2018)

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Sei Morimoto

Masao Sekine

Masao Tanaka

Masao Watanabe

Mohamed Abdul-Jalil Ahmed Masaoud

 

Other publications of authors with the same name

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS., , , and . VLSIC, page 58-59. IEEE, (2012)A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry., , , , , , , , , and . A-SSCC, page 17-20. IEEE, (2016)High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition., , and . IEICE Trans. Electron., 88-C (10): 2001-2008 (2005)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , and . CICC, page 701-704. IEEE, (2009)A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS., , , , , , and . IEEE J. Solid State Circuits, 48 (4): 917-923 (2013)12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM., , , and . VLSI Circuits, page 19-20. IEEE, (2018)1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology., , , , and . VLSIC, page 274-. IEEE, (2015)13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists., , , , and . ISSCC, page 234-235. IEEE, (2014)Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations., , and . IEICE Trans. Electron., 90-C (4): 675-682 (2007)An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm., , , , , , , , , and 3 other author(s). CICC, page 167-170. IEEE, (2002)