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Disambiguation of "Shi, Runbin"

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A Heterogeneous System for Real-Time Detection with AdaBoost.

, , , , , and . HPCC/SmartCity/DSS, page 839-843. IEEE Computer Society, (2016)

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Zhanjun Shi

Jian Shi

Renhu Shi

Shi Li

Jianmin Shi

 

Other publications of authors with the same name

Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework., , , , , , , and . CoRR, (2020)A programmable baseband processor for massive MIMO uplink multi-user detection., , , , , and . ASICON, page 1-4. IEEE, (2015)FTDL: An FPGA-tailored Architecture for Deep Learning Systems., , , , , and . FPGA, page 320. ACM, (2020)Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers., , , , and . ICLR, OpenReview.net, (2020)A Heterogeneous System for Real-Time Detection with AdaBoost., , , , , and . HPCC/SmartCity/DSS, page 839-843. IEEE Computer Society, (2016)CSB-RNN: a faster-than-realtime RNN acceleration framework with compressed structured blocks., , , , , , , , and . ICS, page 24:1-24:12. ACM, (2020)Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory., , , and . FPT, page 56-63. IEEE, (2017)ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures., , , , , , and . CoRR, (2022)Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework., , , , , , , and . HPCA, page 208-220. IEEE, (2021)FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability., , , , , , and . DAC, page 1-6. IEEE, (2020)