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Disambiguation of "Lee, Hsien-Hsin S."

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DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference.

, , , , , , , , and . ISCA, page 982-995. IEEE, (2020)

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Po-Hsien Lee

Simon S Lee

Wenjung Hsing

Chi-Wu Hsing

Linda Hsien

 

Other publications of authors with the same name

An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems., , and . FPL, page 47-53. IEEE, (2007)Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (1): 1-13 (2013)SimWare: A Holistic Warehouse-Scale Computer Simulator., and . Computer, 45 (9): 48-55 (2012)Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (1): 38-52 (2007)Chasing Carbon: The Elusive Environmental Footprint of Computing., , , , , , , and . HPCA, page 854-867. IEEE, (2021)SHARK: Architectural support for autonomic protection against stealth by rootkit exploits., and . MICRO, page 106-116. IEEE Computer Society, (2008)Chasing Carbon: The Elusive Environmental Footprint of Computing., , , , , , , and . IEEE Micro, 42 (4): 37-47 (2022)Energy-Efficient Network Memory for Ubiquitous Devices., , , , and . IEEE Micro, 23 (5): 60-70 (2003)Profile-guided microarchitectural floor planning for deep submicron processor design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1289-1300 (2006)Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching., , , and . ACM Trans. Archit. Code Optim., 7 (1): 3:1-3:35 (2010)