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A Programmable Imager for Very High Speed Cellular Signal Processing., , , , and . VLSI Signal Processing, 23 (2-3): 305-318 (1999)Data Matrix Code Recognition Using the Eye-RIS Vision System., , , , , , and . ISCAS, page 1214. IEEE, (2007)CMOS design of focal plane programmable array processors., , , , and . ESANN, page 57-62. (2001)Analog weight buffering strategy for CNN chips., , , , and . ISCAS (3), page 522-525. IEEE, (2003)An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision., , , and . Journal of Circuits, Systems, and Computers, 12 (6): 675-690 (2003)A 1000FPS@128×128 vision processor with 8-bit digitized I/O., , , and . ESSCIRC, page 61-64. IEEE, (2003)Retinal Processing Emulation in a Programmable 2-Layer Analog Array Processor CMOS Chip., , , , and . NIPS, page 1099-1106. MIT Press, (2002)A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques., , , , and . ISCAS, page 970-973. IEEE, (1993)A bio-inspired two-layer mixed-signal flexible programmable chip for early vision., , , , , , , and . IEEE Trans. Neural Networks, 14 (5): 1313-1336 (2003)An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs., , , , , , , , , and . ECCTD, page 1-4. IEEE, (2013)