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A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , and . J. Electron. Test., 17 (3-4): 283-290 (2001)Bridging defects resistance in the metal layer of a CMOS process., , and . J. Electron. Test., 8 (1): 35-46 (1996)IDDQ testing: state of the art and future trends., , , , and . Integr., 26 (1-2): 167-196 (1998)Statistical analysis of 6T SRAM data retention voltage under process variation., and . DDECS, page 365-370. IEEE Computer Society, (2011)Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell., , , , , and . DATE, page 447-452. ACM, (2015)Minimizing the Number of Test Configurations for Different FPGA Families., , , and . Asian Test Symposium, page 363-368. IEEE Computer Society, (1999)Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study., , , and . ETW, page 146-151. IEEE Computer Society, (1999)IS-FPGA : a new symmetric FPGA architecture with implicit scan., , , , and . ITC, page 924-931. IEEE Computer Society, (2001)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST., , , , , and . ITC, page 814-823. IEEE Computer Society, (2002)Analysis of redundant structures in combinational circuits., and . VTS, page 21-23. IEEE Computer Society, (1993)