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A new architecture of companding integrator for CMOS current-mode analog filters.

, , and . ICECS, page 446-449. IEEE, (2010)

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CMOS analog current-mode multiplier based on the advanced compact MOSFET model., , and . ISCAS (2), page 1020-1023. IEEE, (2005)Improving a MOSFET model for design by hand., , , , and . LASCAS, page 1-4. IEEE, (2017)Improvements on the Design of the Low Saturation Onset Transistor., , , and . ICECS, page 1-4. IEEE, (2020)A compact charge-based MOSFET model for circuit simulation., , , and . ICECS, page 491-494. IEEE, (1998)On the adequate transistor modeling for optimal design of CMOS OTA., , , and . SBCCI, page 27-31. ACM, (2005)CMOS analog four-quadrant multiplier free of voltage reference generators., , , , , , and . SBCCI, page 27. ACM, (2019)An experiment set-up for analysis of lateralization judgments of binaural stimuli., , , and . I2MTC, page 1507-1511. IEEE, (2013)An Explicit MOSFET Model for Analog Circuit Simulation., , , and . ISCAS, page 1592-1595. IEEE, (1995)A single-piece charge-based model for the output conductance of MOS transistors., , , and . ICECS, page 545-548. IEEE, (1998)A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering., , , and . SBCCI, page 1-6. IEEE, (2020)