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A two-phase floorplanning approach for Application-specific Network-on-Chip.

, , , and . ASICON, page 1-4. IEEE, (2013)

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A two-phase floorplanning approach for Application-specific Network-on-Chip., , , and . ASICON, page 1-4. IEEE, (2013)Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning., , , , and . ICCT, page 301-305. IEEE, (2021)Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection., , , and . ICCT, page 1555-1559. IEEE, (2022)A Hybrid CNN Compression Approach for Hardware Acceleration., , , , and . ICCT, page 1546-1550. IEEE, (2022)An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units., , , and . ICCT, page 1521-1525. IEEE, (2022)Design and Implementation of LSTM Accelerator Based on FPGA., , , , , and . ICCT, page 1675-1679. IEEE, (2020)DimNoC: a dim silicon approach towards power-efficient on-chip network., , , , and . DAC, page 10:1-10:6. ACM, (2015)Differential Fault Attack for the Iterative Operation of AES-192 Key Expansion., , , , , and . ICCT, page 1156-1160. IEEE, (2020)Design and Implementation of OpenCL-Based FPGA Accelerator for YOLOv2., , , , , and . ICCT, page 1004-1007. IEEE, (2021)An Anti-DPA Elliptic Curve Cryptography Scalar Multiplier with Randomized Base Point., , , , , and . ICCT, page 100-104. IEEE, (2021)