( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.

, , , , и . APCCAS, стр. 143-145. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Pey-Jin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

 

Другие публикации лиц с тем же именем

MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging., , , , и . APCCAS, стр. 143-145. IEEE, (2016)Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation., , , , и . ISOCC, стр. 109-110. IEEE, (2019)Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design., , , , , и . Sensors, 22 (15): 5696 (2022)Low Power Multipliers Using Enhenced Row Bypassing Schemes., , , и . SiPS, стр. 136-141. IEEE, (2007)Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme., , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 361-366 (2012)Low Power Multiplier Designs Based on Improved Column Bypassing Schemes., , , и . APCCAS, стр. 594-597. IEEE, (2006)Semantic Lung Segmentation Using Convolutional Neural Networks., , , и . Bildverarbeitung für die Medizin, стр. 75-80. Springer, (2020)A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications., , , , и . ICCE-TW, стр. 1-2. IEEE, (2021)A high speed and energy efficient full adder design using complementary & level restoring carry logic., , , и . ISCAS, IEEE, (2006)Low power 10-transistor full adder design based on degenerate pass transistor logic., , и . ISCAS, стр. 496-499. IEEE, (2012)