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Logic gates dynamic modeling by means of an ultra-compact MOS model., , and . ISCAS, page 3250-3253. IEEE, (2012)TG Master-Slave FFs: High-speed optimization., , and . ISCAS, page 554-557. IEEE, (2011)Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency., , and . ISCAS, page 321-324. IEEE, (2010)An ultra-compact MOS model in nanometer technologies., , and . ECCTD, page 520-523. IEEE, (2011)Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design., , and . ECCTD, page 61-64. IEEE, (2009)Optimum clock slope for flip-flops within a clock domain: Analysis and a case study., , and . ICECS, page 275-278. IEEE, (2009)Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model., , and . ECCTD, page 512-515. IEEE, (2011)Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits., , and . ISCAS, page 3150-3153. IEEE, (2009)PVT variations in differential flip-flops: A comparative analysis., , and . ECCTD, page 1-4. IEEE, (2015)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 725-736 (2011)