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An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).

M. Amoo, Y. Kim, V. Alford, S. Jadhav, N. El-Bathy, and C. Jr.. FPGA, page 263. ACM, (2015)

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Shrikant Manjrekar

Sanjay Jadhav

Vinod Jadhav

Priyadarshani Jadhav

Kedar Shrikant Ranade

Other publications of authors with the same name

Design & Verification of AMBA AHB-Lite Memory Controller.A. Kommineni, M. Gundu, Y. Kim, and S. Jadhav. CCWC, page 1307-1312. IEEE, (2023)Reconfigurable Fault Tolerant Processor on a SRAM based FPGA.B. Shashidhara, S. Jadhav, and Y. Kim. EIT, page 151-154. IEEE, (2020)RTL to GDS Implementation and Verification of UART using UVM and OpenROAD.P. Bhatt, D. Joshi, and S. Jadhav. CCWC, page 713-720. IEEE, (2024)An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).M. Amoo, Y. Kim, V. Alford, S. Jadhav, N. El-Bathy, and C. Jr.. FPGA, page 263. ACM, (2015)Smart City Service Acceleration on FPGAs.Y. Kim, M. Garcia, A. Chen, N. Wong, S. Jadhav, and C. Jr.. BigDataService, page 243-248. IEEE Computer Society, (2017)Project based courses in control cyber physical system co-design.Y. Kim, A. Chen, S. Jadhav, C. Jr., T. Le, and P. Hsu. WESE, page 4:1-4:4. ACM, (2016)Dataflow to Hardware Synthesis Framework on FPGAs.Y. Kim, S. Jadhav, and C. Jr.. SBAC-PAD (Workshops), page 91-96. IEEE Computer Society, (2016)Improving the Accuracy of Arctan for Face Detection.Y. Kim, H. Shahdoost, S. Jadhav, and C. Jr.. FCCM, page 202. IEEE Computer Society, (2017)An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs.J. Naher, C. Gloster, C. Doss, and S. Jadhav. FCCM, page 205. IEEE, (2020)Implementating Grid Portal for Scientific Job Submission.A. Gangarde, and S. Jadhav. FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 347-353. Springer, (2010)

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Disambiguation of "Jadhav, Shrikant"

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An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).

Please choose a person to relate this publication to

Shrikant Manjrekar

Sanjay Jadhav

Vinod Jadhav

Priyadarshani Jadhav

Kedar Shrikant Ranade

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jadhav, Shrikant"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).

Please choose a person to relate this publication to

Shrikant Manjrekar

Sanjay Jadhav

Vinod Jadhav

Priyadarshani Jadhav

Kedar Shrikant Ranade

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).