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Highly linear 100 MHz CMOS programmable gain amplifiers.

, and . ISCAS (1), page 647-650. IEEE, (2001)

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Highly linear 100 MHz CMOS programmable gain amplifiers., and . ISCAS (1), page 647-650. IEEE, (2001)A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques., and . CICC, page 1-4. IEEE, (2018)A statistical background calibration technique for flash analog-to-digital converters., and . ISCAS (1), page 125-128. IEEE, (2004)A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration., , and . CICC, page 209-212. IEEE, (2006)An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch., , , , , , , and . ESSCIRC, page 83-86. IEEE, (2019)A digital background calibration technique for pipelined analog-to-digital converters., , and . ISCAS (1), page 881-884. IEEE, (2003)A robust background calibration technique for switched-capacitor pipelined ADCs., and . ISCAS (2), page 1374-1377. IEEE, (2005)Multi-level memory systems using error control codes., , , , and . ISCAS (2), page 393-396. IEEE, (2004)A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter., and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (5): 1106-1117 (2017)On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC., , , , , , , , and . ASP-DAC, page 352-357. ACM, (2023)