( en | de | ru )

 

Disambiguation of "Balachandran, Shankar"

Author of the publication

copydeleteadd this publication to your clipboard
Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute.

, , , , , , , and . CoRR, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Prakash Balachandran

Muthuswami Balachandran

Shankar Vembu

Shankar Krishnan

Shankar Agharkar

 

Other publications of authors with the same name

Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute., , , , , , , and . CoRR, (2020)A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement., and . VLSID, page 417-422. IEEE Computer Society, (2015)The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency., , , , and . HotPower, USENIX Association, (2012)LPScan: An algorithm for supply scaling and switching activity minimization during test., , , and . ICCD, page 463-466. IEEE Computer Society, (2013)TCPT - Thread criticality-driven prefetcher throttling., and . PACT, page 399. IEEE Computer Society, (2013)A-priori wirelength and interconnect estimation based on circuit characteristics., and . SLIP, page 77-84. ACM, (2003)Fast-SL: An efficient algorithm to identify synthetic lethal reaction sets in metabolic networks, , and . (Jul 15, 2014)Set-Cover Heuristics for Two-Level Logic Minimization., and . VLSI Design, page 197-202. IEEE Computer Society, (2012)On metrics for comparing interconnect estimation methods for FPGAs., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (4): 381-385 (2004)Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control., and . DATE, page 1-6. European Design and Automation Association, (2014)