( en | de | ru )

 

Disambiguation of "Goutis, Costas E."

Author of the publication

copydeleteadd this publication to your clipboard
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (12): 1362-1366 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Peter Costas

Costas Averkiou

Costas Higoumenakis

Ilse Costas

Costas Panayotakis

 

Other publications of authors with the same name

Implementation of HSSec: a high-speed cryptographic co-processor., , , and . ETFA, page 625-631. IEEE, (2007)High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)Spectra using data distribution and covariance modelling., , and . ICASSP, page 642-645. IEEE, (1984)A VLSI synthesis tool for complementary output delta modulation FIR filters., , , and . Microprocess. Microprogramming, 34 (1-5): 139-142 (1992)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , and . IPDPS, IEEE Computer Society, (2005)A low power fault secure timer implementation based on the Gray encoding scheme., , , and . ICECS, page 537-540. IEEE, (2002)Fault secure binary counter design., , and . ICECS, page 1659-1662. IEEE, (1999)System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors., , , and . ICECS, page 1733-1736. IEEE, (1999)High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)On the computation of the prime factor DST., , , and . Signal Process., 42 (3): 231-236 (1995)