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Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors.

J. Ríos, A. Armejach, G. Khattak, E. Petit, S. Vallecorsa, and M. Casas. ICMLA, page 49-56. IEEE, (2020)

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Adria Wehser

Johann Adrian

Joachim Adrian

Werner Adrian

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Circuit design of a dual-versioning L1 data cache.A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero. Integr., 45 (3): 237-245 (2012)Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.O. Arcas-Abella, A. Armejach, T. Hayes, G. Malazgirt, O. Palomar, B. Salami, and N. Sönmez. Comput. Sci. Eng., 18 (1): 80-87 (2016)A BF16 FMA is All You Need for DNN Training.J. Ríos, A. Armejach, E. Petit, G. Henry, and M. Casas. ARITH, page 9. IEEE, (2022)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.A. Armejach, A. Seyedi, J. Gil, I. Hur, A. Cristal, O. Unsal, and M. Valero. PACT, page 361-371. IEEE Computer Society, (2011)Design trade-offs for emerging HPC processors based on mobile market technology.A. Armejach, M. Casas, and M. Moretó. J. Supercomput., 75 (9): 5717-5740 (2019)Using Arm's scalable vector extension on stencil codes.A. Armejach, H. Caminal, J. Cebrian, R. Langarita, R. González-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, and M. Moretó. J. Supercomput., 76 (3): 2039-2062 (2020)Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.R. Langarita, A. Armejach, J. Setoain, P. Ibáñez-Marín, J. Alastruey-Benedé, and M. Moretó. IEEE ACM Trans. Comput. Biol. Bioinform., 19 (1): 355-368 (2022)Circuit design of a dual-versioning L1 data cache for optimistic concurrency.A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero. ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)Transactional prefetching: narrowing the window of contention in hardware transactional memory.A. Negi, A. Armejach, A. Cristal, O. Unsal, and P. Stenström. PACT, page 181-190. ACM, (2012)HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.A. Armejach, A. Negi, A. Cristal, O. Unsal, P. Stenström, and T. Harris. HiPC, page 196-205. IEEE Computer Society, (2013)

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Disambiguation of "Armejach, Adrià"

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Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors.

Please choose a person to relate this publication to

Adria Wehser

Johann Adrian

Joachim Adrian

Werner Adrian

Werner Adrian

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Armejach, Adrià"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors.

Please choose a person to relate this publication to

Adria Wehser

Johann Adrian

Joachim Adrian

Werner Adrian

Werner Adrian

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors.