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Disambiguation of "Zheng, Long"

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FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers.

, , , , , , , and . J. Comput. Sci. Technol., 36 (5): 1051-1070 (2021)

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Zheng-long Ren

Zheng-Zheng Kuang

Long Chen

Long Ling

Li Long

 

Other publications of authors with the same name

A Scalable Multiprocessor Architecture for Pervasive Computing., , , , , , , , and . GPC, volume 6646 of Lecture Notes in Computer Science, page 42-51. Springer, (2011)A Hint Frequency Based Approach to Enhancing the I/O Performance of Multilevel Cache Storage Systems., , , , , , and . J. Comput. Sci. Technol., 32 (2): 312-328 (2017)The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead., , , , , and . NPC, volume 6289 of Lecture Notes in Computer Science, page 358-372. Springer, (2010)CPU + GPU scheduling with asymptotic profiling., , , and . Parallel Comput., 40 (2): 107-115 (2014)SumPA: Efficient Pattern-Centric Graph Mining with Pattern Abstraction., , , , , and . PACT, page 318-330. IEEE, (2021)Accelerating Graph Convolutional Networks Using Crossbar-based Processing-In-Memory Architectures., , , , , , and . HPCA, page 1029-1042. IEEE, (2022)AFaVS: Accurate Yet Fast Version Switching for Graph Processing Systems., , , , , , , , , and . ICDE, page 53-66. IEEE, (2023)PDAS: Improving network pruning based on Progressive Differentiable Architecture Search for DNNs., , , , and . Future Gener. Comput. Syst., (2023)Accelerating Loop-Oriented RTL Simulation With Code Instrumentation., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4985-4998 (December 2023)Balanced bipartite graph based register allocation for network processors in mobile and wireless networks., , , , and . Mob. Inf. Syst., 6 (1): 65-83 (2010)