Author of the publication

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration.

, , , , , , , and . IEEE J. Solid State Circuits, 55 (12): 3210-3224 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

High speed pipelined ADCs: Fundamentals and variants.. CICC, page 1-145. IEEE, (2018)Analysis and Comparison of High-Resolution GS/s Samplers in Advanced BiCMOS and CMOS., , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (5): 532-536 (2018)A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration., , , , , , , and . IEEE J. Solid State Circuits, 55 (12): 3210-3224 (2020)Correction of operational amplifier gain error in pipelined A/D converters., and . ISCAS (1), page 568-571. IEEE, (2001)A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration., , , , , , , , , and 3 other author(s). ISSCC, page 292-293. IEEE, (2010)16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration., , , , , , , , , and . ISSCC, page 250-252. IEEE, (2020)A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 49 (12): 2857-2867 (2014)A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither., , , , , , , , , and 7 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter., , , , , , and . CICC, page 391-394. IEEE, (2005)