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Disambiguation of "Bystrov, Alexandre V."

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STG Optimisation in the Direct Mapping of Asynchronous Circuits .

, , and . DATE, page 10932-10939. IEEE Computer Society, (2003)

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Evgenia Bystrov

V Saile

V Geoffroy

V Wittwer

V Ustinov

 

Other publications of authors with the same name

Petri Net Modelling of Estelle-specified Communication Protocols., , , , , and . PaCT, volume 964 of Lecture Notes in Computer Science, page 94-108. Springer, (1995)On-chip structures for timing measurement and test., , , , and . Microprocess. Microsystems, 27 (9): 473-483 (2003)Selected Articles from the IEEE LPonTR 2012 Workshop.. J. Low Power Electron., 9 (1): 118 (2013)Application of Modified Coloured Petri Nets to Modeling and Verification of SDL Specified Communication Protocols., , , , , , , , and . CSR, volume 4649 of Lecture Notes in Computer Science, page 303-314. Springer, (2007)A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 471-480. Springer, (2004)Analysis of the oscillation problem in tri-flops., , , and . ISCAS (1), page 381-384. IEEE, (2002)Synthesis of Asynchronous Circuits with Predictable Latency., and . IWLS, page 239-243. (2002)Phase-Encoding for On-Chip Signalling., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 535-545 (2008)Implementing Model Checking and Equivalence Checking for Time Petri Nets by the RT-MEC Tool., and . PaCT, volume 1662 of Lecture Notes in Computer Science, page 194-199. Springer, (1999)STG Optimisation in the Direct Mapping of Asynchronous Circuits ., , and . DATE, page 10932-10939. IEEE Computer Society, (2003)