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Automatic high-level synthesis of multi-threaded hardware accelerators., , и . FPL, стр. 1-4. IEEE, (2014)Experiences Building an MLIR-Based SYCL Compiler., , , , , , , и . CGO, стр. 399-410. IEEE, (2024)Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis., и . UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld, стр. 1157-1164. IEEE Computer Society, (2016)SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis., , , , , и . FPT, стр. 36-44. IEEE, (2019)On Demand Specialization of SYCL Kernels with Specialization Constant Length Allocations (SCLA)., , , , , , и . IWOCL, стр. 21:1-21:2. ACM, (2024)Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling., , , , , и . Euro-Par, том 11725 из Lecture Notes in Computer Science, стр. 170-183. Springer, (2019)The Scale4Edge RISC-V Ecosystem., , , , , , , , , и 17 other автор(ы). DATE, стр. 808-813. IEEE, (2022)Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language., , , и . CGO, стр. 278-279. IEEE, (2019)NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management., , , , , и . EDBT, стр. 457-460. OpenProceedings.org, (2018)Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators., , , , , и . ICCD, стр. 350-357. IEEE Computer Society, (2018)