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Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing.. Syst. Comput. Jpn., 21 (5): 29-38 (1990)Aliasing Probabilities and Weight Distributions of Several Codes., and . Syst. Comput. Jpn., 20 (9): 81-88 (1989)Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters., , , , and . Asian Test Symposium, page 190-195. IEEE Computer Society, (2004)Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage., , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (2012)Analysis of Probabilistic Trapezoid Protocol for Data Replication., , , , and . DSN, page 782-791. IEEE Computer Society, (2005)Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation., , and . ITC, page 1-8. IEEE, (2017)Analysis and proposal of signature circuits for LSI testing.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 84-90 (1988)Analysis of error-masking and X-masking probabilities for convolutional compactors., , and . ITC, page 10. IEEE Computer Society, (2005)A defect-tolerant design for mask ROMs., , and . VTS, page 171-175. IEEE Computer Society, (1992)Experimental fault analysis of 1 Mb SRAM chips., , and . VTS, page 31-36. IEEE Computer Society, (1997)