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Disambiguation of "Fulde, Michael"

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Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.

, , , , , , , , , , , and . ESSCIRC, page 145-148. IEEE, (2005)

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Michael Fulde

Reinhard Fulde

Walter Fulde

Katrin Fulde

Elenor Fulde

 

Other publications of authors with the same name

Design of Low-Voltage Bandgap Reference Circuits in Multi-Gate CMOS Technologies., , , and . ISCAS, page 2537-2540. IEEE, (2009)Layout options for stability tuning of SRAM cells in multi-gate-FET technologies., , , , , , , , , and 3 other author(s). ESSCIRC, page 392-395. IEEE, (2007)LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (8): 467-471 (2011)Dynamic state-retention flip flop for fine-grained sleep-transistor scheme., , , , , , , , , and 2 other author(s). ESSCIRC, page 145-148. IEEE, (2005)Analog design challenges and trade-offs using emerging materials and devices., , , , , , , , , and . ESSCIRC, page 123-126. IEEE, (2007)A Nonlinear Switched State-Space Model for Capacitive RF DACs., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (6): 1342-1353 (2017)An aging suppression and calibration approach for differential amplifiers in advanced CMOS technologies., , , and . ESSCIRC, page 251-254. IEEE, (2011)Advances in Multi-Gate MOSFET Circuit Design., , , , , , , , , and 2 other author(s). ICECS, page 186-189. IEEE, (2007)Assessment of the impact of technology scaling on the performance of LC-VCOs., , , , , and . ESSCIRC, page 364-367. IEEE, (2009)Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits., , and . ISCAS, page 1249-1252. IEEE, (2007)