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A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.

, , , , and . MTDT, page 65-69. IEEE Computer Society, (2004)

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A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2184-2194 (2011)MRAM Defect Analysis and Fault Modeli., , , , , , and . ITC, page 124-133. IEEE Computer Society, (2004)Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning., , , and . EDAC-ETC-EUROASIC, page 661. IEEE Computer Society, (1994)A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories., , , , and . MTDT, page 65-69. IEEE Computer Society, (2004)A Probabilistic Testability Measure for Delay Faults., and . DAC, page 440-445. ACM, (1991)CAD reference flow for 3D via-last integrated circuits., , , , and . ASP-DAC, page 187-192. IEEE, (2010)A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs., , , , , and . ITC, page 1-8. IEEE Computer Society, (2006)Identification of robust untestable path delay faults., , and . Asian Test Symposium, page 229-. IEEE Computer Society, (1995)Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle., , , and . Asian Test Symposium, page 106-111. IEEE Computer Society, (2005)Fault diagnosis of odd-even sorting networks., , , and . Asian Test Symposium, page 288-. IEEE Computer Society, (1997)