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Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (12): 2569-2582 (2009)

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A new efficient SC integrator scheme for high-speed low-power applications., , and . I. J. Circuit Theory and Applications, 40 (8): 733-744 (2012)Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.. ICECS, page 491-494. IEEE, (2003)Settling Time Optimization for Three-Stage CMOS Amplifier Topologies., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (12): 2569-2582 (2009)Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students., , , , , , , , , and . FIE, page 1-2. IEEE Computer Society, (2012)Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (3): 618-630 (2010)Design criterion for high-speed low-power SC circuits., , and . I. J. Circuit Theory and Applications, 39 (10): 1067-1078 (2011)Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers., , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 318-327. Springer, (2008)Design methodology of nested-Miller amplifiers for small capacitive loads., , and . ECCTD, page 655-658. IEEE, (2007)A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 311-318. Springer, (2006)Settling Time Minimization of Operational Amplifiers., , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 107-116. Springer, (2007)