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Disambiguation of "Noguchi, Hiroki"

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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

, , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)

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Hiroki Takahashi

Masahiro Noguchi

Hiroki Kawamura

Yoshiko Noguchi

Shozo Noguchi

 

Other publications of authors with the same name

Data-Intensive Sound Acquisition System with Large-scale Microphone Array., , , , , and . J. Inf. Process., (2011)A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition., , , , , , , , , and . IEICE Trans. Electron., 94-C (4): 448-457 (2011)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing., , , , , , and . ISVLSI, page 107-112. IEEE Computer Society, (2007)Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video., , , , , , and . FPL, page 608-611. IEEE Computer Society, (2010)Live demonstration: Intelligent ubiquitous sensor network for sound acquisition., , , , and . ISCAS, page 1413. IEEE, (2010)Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures., , , , , and . ISIC, page 316-319. IEEE, (2014)A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system., , , and . FPT, page 341-344. IEEE, (2008)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system., , , , and . INTERSPEECH, page 1483-1486. ISCA, (2009)