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Inference of Suitable for Required Specification Analog Circuit Topology using Deep Learning., , , и . ISPACS, стр. 131-134. IEEE, (2018)New architecture for envelope-tracking power amplifier for base station., , , , , , , и . APCCAS, стр. 296-299. IEEE, (2008)Delay-time suppression technique for DC/DC buck converter using voltage mode PWM control., , , , , и . ISPACS, стр. 758-763. IEEE, (2017)Automatic design of doubly-terminated RC polyphase filters by using distributed genetic algorithm., , , , , и . ASICON, стр. 1-4. IEEE, (2015)Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization., , , , , и . ASICON, стр. 1-4. IEEE, (2015)SAR ADC Algorithm with Redundancy and Digital Error Correction., , , , , , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (2): 415-423 (2010)Single inductor dual output DC-DC converter design with exclusive control., , , , , , , , , и 6 other автор(ы). APCCAS, стр. 436-439. IEEE, (2012)DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control., , , , , , , , , и 4 other автор(ы). APCCAS, стр. 65-68. IEEE, (2012)Automatic design of RC polyphase filters with small element value spread using genetic algorithm., , , , , и . ISPACS, стр. 303-306. IEEE, (2015)Rail-to-rail OTA utilizing linear V-I conversion circuit using single channel MOSFETs for input stage., и . ECCTD, стр. 31-34. IEEE, (2005)