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Disambiguation of "Ni, Leibin"

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A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks.

, , , , , and . ASICON, page 1-4. IEEE, (2019)

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Ying Ni

Pedestrian safety at urban signalised intersections. TU Darmstadt, (2009)

Yi Ni

Ji Ni

Xiaoju Ni

Jianbing Ni

 

Other publications of authors with the same name

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node., , , , , , and . DATE, page 1083-1084. IEEE, (2022)AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADC., , , , , and . DATE, page 1-6. IEEE, (2024)An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar., , , , , , and . ISLPED, page 1-6. IEEE, (2017)A 3D multi-layer CMOS-RRAM accelerator for neural network., , , , , , and . 3DIC, page 1-5. IEEE, (2016)On-line machine learning accelerator on digital RRAM-crossbar., , and . ISCAS, page 113-116. IEEE, (2016)A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks., , , , , and . ASICON, page 1-4. IEEE, (2019)SEALS: sensitivity-driven efficient approximate logic synthesis., , , , , , , , , and . DAC, page 439-444. ACM, (2022)Racetrack memory-based encoder/decoder for low-power interconnect architectures., , , and . SAMOS, page 281-287. IEEE, (2016)LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network., , and . SoCC, page 280-285. IEEE, (2017)High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table., , , , , and . DATE, page 1-6. IEEE, (2023)