Author of the publication

A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs.

, , and . ISCAS (5), page 4831-4834. IEEE, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

High-performance ADC linearity test using low-precision signals in non-stationary environments., , , , and . ITC, page 10. IEEE Computer Society, (2005)Testing of Precision DACs Using Low-Resolution ADCs with Dithering., , , and . ITC, page 1-10. IEEE Computer Society, (2006)Fast-switching adaptive bandwidth frequency synthesizer using a loop filter with switched zero-resistor array., and . ISCAS (6), page 5373-5376. IEEE, (2005)Inflection point correction for voltage references., , and . ISCAS (1), page 649-652. IEEE, (2003)A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider., and . ISCAS (1), page 256-259. IEEE, (2001)An adaptive, truly background calibration method for high speed pipeline ADC design., , and . ISCAS (6), page 6190-6193. IEEE, (2005)A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs., , and . ISCAS (5), page 4831-4834. IEEE, (2005)An SoC compatible linearity test approach for precision ADCs using easy-to-generate sinusoidal stimuli., , , and . ISCAS (1), page 928-931. IEEE, (2004)Testing high resolution ADCs using deterministic dynamic element matching., , , and . ISCAS (1), page 920-923. IEEE, (2004)A low-voltage compatible two-stage amplifier with ≥120 dB gain in standard digital CMOS., , and . ISCAS (1), page 353-356. IEEE, (2003)