Author of the publication

Fast BIST of I/O Pin AC specifications and inter-chip delays.

, , and . ITC, page 1-8. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring., , , , , and . ITC, page 258-267. IEEE Computer Society, (2001)Practices in High-Speed IO testing., and . ETS, page 1-8. IEEE, (2016)Manufacturability and Testability Oriented Synthesis., , and . VLSI Design, page 185-191. IEEE Computer Society, (2000)Practices in Testing of Mixed-Signal and RF SoCs., and . Asian Test Symposium, page 467. IEEE Computer Society, (2005)Challenges in High Speed Interface Testing., and . Asian Test Symposium, page 468. IEEE Computer Society, (2005)CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator., , and . PDPTA, page 109-112. CSREA Press, (1996)Test and Debug of Networking SoCs: A Case Study., , , and . VTS, page 121-126. IEEE Computer Society, (2000)IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.. ITC, page 543-550. IEEE Computer Society, (2004)Maximizing Wafer Productivity Through Layout Optimization., , , , and . VLSI Design, page 192-197. IEEE Computer Society, (2000)Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation., and . Annual Simulation Symposium, page 64-74. IEEE Computer Society, (1997)