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Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery., , , и . DAC, стр. 34:1-34:6. ACM, (2017)Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning., , и . ITC, стр. 1-8. IEEE Computer Society, (2009)Enhancing signal controllability in functional test-benches through automatic constraint extraction., , и . ITC, стр. 1-10. IEEE Computer Society, (2007)Full chip false timing path identification: applications to the PowerPCTM microprocessors., , , и . DATE, стр. 514-519. IEEE Computer Society, (2001)Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling., , , , и . MTV, стр. 3-8. IEEE Computer Society, (2009)An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology., , , , и . ASP-DAC, стр. 163-168. IEEE, (2012)Introduction to special section on verification challenges in the concurrent world., , , , и . ACM Trans. Design Autom. Electr. Syst., 17 (3): 19:1-19:3 (2012)A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications., , , и . HLDVT, стр. 134-141. IEEE Computer Society, (2001)A Mechanized Refinement Framework for Analysis of Custom Memories., и . FMCAD, стр. 239-242. IEEE Computer Society, (2007)Striking a balance between SoC security and debug requirements., и . SoCC, стр. 368-373. IEEE, (2016)