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Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.

, , , , , и . ReConFig, стр. 1-8. IEEE, (2017)

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Johannes Blochwitz

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Christian Blochwitz

Reinhard Blochwitz

Reinhard Blochwitz

 

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Hardware-Accelerated Index Construction for Semantic Web., , , , , , и . FPT, стр. 278-281. IEEE, (2018)StreamGrid - An AXI-Stream-Compliant Overlay Architecture., , , и . ARC, том 12700 из Lecture Notes in Computer Science, стр. 156-170. Springer, (2021)Adaptive allocation of default router paths in Network-on-Chips for latency reduction., , и . HPCS, стр. 140-147. IEEE, (2016)A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip., , , , и . ReCoSoC, стр. 1-8. IEEE, (2016)Continuous live-tracing as debugging approach on FPGAs., , , и . ReConFig, стр. 1-8. IEEE, (2017)A comparative survey of open-source application-class RISC-V processor implementations., , , , , , , , и . CF, стр. 12-20. ACM, (2021)Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS., , , , , и . ReConFig, стр. 1-8. IEEE, (2017)Hardware-accelerated pose estimation for embedded systems using Vivado HLS., , , , и . ReConFig, стр. 1-7. IEEE, (2016)Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs., , , и . NORCAS, стр. 1-4. IEEE, (2015)RemEduLa - Remote Education Laboratory for FPGA Design Technology., , , , , и . ISCAS, стр. 1773-1777. IEEE, (2022)