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A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation.

, , , and . CIT, page 184-191. IEEE Computer Society, (2017)

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MDS array codes with optimal rebuilding., , and . ISIT, page 1240-1244. IEEE, (2011)Patterned cells for phase change memories., , , and . ISIT, page 2333-2337. IEEE, (2011)A Channel Estimation Scheme for MIMO-MC-CDMA Downlink in High Mobility Environments., and . IEICE Trans. Commun., 88-B (3): 1282-1286 (2005)Protecting Mass Data Basing on Small Trusted Agent., , , and . ISPEC, volume 3439 of Lecture Notes in Computer Science, page 362-373. Springer, (2005)A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology., , , and . VLSI-SoC, page 216-221. IEEE, (2006)An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators., , , , and . ISCAS, page 1-5. IEEE, (2019)Adaptive VC Partitioning for NoCs in GPGPUs., , , , , , and . ISCAS, page 1-5. IEEE, (2018)A Novel Vertical Fragmentation Method for Privacy Protection Based on Entropy Minimization in a Relational Database., , , and . Symmetry, 10 (11): 637 (2018)An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network., , , and . Sci. China Inf. Sci., 56 (7): 1-20 (2013)Dynamic Power Estimation with Hardware Performance Counters Support on Multi-core Platform., , , and . ACA, volume 451 of Communications in Computer and Information Science, page 177-189. Springer, (2014)